1. Field of the Invention
The invention relates to a circuit configuration and a method for reducing the 1/f noise of MOSFETs in an electronic circuit, in particular in an integrated circuit. The electronic circuit has at least one MOSFET. One or a plurality or all of the MOSFETs are assigned at least one DC current and/or at least one DC voltage source for setting constant operating point(s) of the MOSFET(s). In the method for reducing the 1/f noise of MOSFETs in the electronic circuit, constant operating points are set for the MOSFETs.
During signal transmission, it is often necessary to process small signal amplitudes. The limit for the resolution of a signal amplitude in such systems is determined by the noise of the first amplifier stage and can hardly be influenced.
In particular the 1/f noise, dominant at low frequencies, prevents the processing and transmission of small signal amplitudes in this frequency range.
The prior art discloses various measures for alleviating the problems outlined.
Generally, the LF noise is considered as a fixed limit. This fixed limit can be slightly influenced by a skilful choice of the operating points of the circuit and optimization of the technology used. Such a method or a correspondingly favorably chosen circuit configuration does not eliminate or reduce the noise of the noise source, in other words it does not combat the cause of the noise. As is known, in the case of such a method which does not tackle the causes but rather only the effect, the exertion of influence is only very limited. Accordingly, the possibilities of improvement are largely exhausted in the case of these methods.
It is more promising, therefore, if the causes of the low-frequency noise (LF noise) are tackled.
Thus, in semiconductors, metal layers, oxide layers, etc., a noise with a power density spectrum which is inversely proportional to the frequency f also occurs besides other types of noise. This noise is referred to as 1/f noise (flicker noise). The 1/f noise cannot be explained in simple terms, since it has various causes.
The theory which is currently the most widely accepted for the physical cause of the 1/f noise of components is the theory that the 1/f noise in these components is determined by the random charging and discharging of defect states in these components. For the most important component in microelectronics at the present time, the metal oxide semiconductor field-effect transistor (MOSFET), these are essentially defects in the oxide near the interface with the silicon of the channel region. Here, defects which contribute to the noise are primarily those defects whose energy levels lie in the band gap of the oxide, but in the vicinity of the quasi Fermi level of the charge carriers contributing to the current flow. Defects which, as seen in energy terms, lie far away from this energy level in the band gap of the oxide are either completely charged or discharged and thus do not contribute to the noise.
The document I. Bloom, Y. Nemirovsky, “1/f noise reduction of Metal-Oxide-Semiconductor Transistors by Cycling from Inversion to Accumulation”, Applied Physics Letters, Vol. 58 (15), pages 1664–66, Apr. 15, 1991, shows that the charging and discharging times of the defect states causing the noise in the vicinity of the quasi Fermi level are of similar magnitude, whereas the charging and discharging times of defect states that are remote from the quasi Fermi levels differ greatly. Accordingly, such states are virtually exclusively charged or discharged. Accordingly, a defined state is always established.
In the publication presented by I. Bloom and Y. Nemirovsky, a depletion-mode n-channel MOSFET is operated in such a way that the gate-source voltage is changed over between a value of VGS=5 V, which signifies inversion and consequently conduction of the channel, and VGS=−3 V, which signifies accumulation and accordingly a nonconductive channel. The explanations in this document are limited to observing the noise reduction; a possible use in more complex circuits is not investigated.
The printed publication by S. L. J. Gierkink, E. A. M. Klumperink, E. van Tuijl, B. Nauta, “Reducing MOSFET 1/f Noise and Power Consumption by “Switched Biasing”, Proceedings of the 25th European Solid-State-Circuits Conference, pages 154–57, The Hague, The Netherlands, 1999, presents the applicability of the method cited above to a coupled sawtooth ring oscillator.
In that ring oscillator, a MOS transistor is periodically changed over between the following two states:                (1) an “operating state” or “active state” with strong inversion, wherein the transistor contributes to the functional operation of the circuit (in other words, supplies a bias current.        (2) a “quiescent state” or “inactive state” in or in the vicinity of the accumulation state, for practical purposes VGS=0 V. In this state, the MOS transistor is not in operation.        
The advantage of that circuit configuration is that, on the one hand, the energy consumption is reduced in the quiescent state, although what is much more important is that the 1/f noise of the MOS transistor is reduced during the active state.
This document already points out the limited area of use for the method or the circuit configuration. Thus, the authors point out in the printed publication that the method can be employed only when “a bias current is only needed during certain time intervals or because the signal processing does not take place continuously.”